1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to phase interpolating to generate signals within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. Sometimes within such communication systems, there is a need to perform phase interpolation of signals (e.g., by changing the phase of such signals or by generating a signal having a particular phase). For example, within a wide variety of applications (e.g., serializers, de-serializers, and/or other communication devices, etc.), there may be a need to generate a signal having a desired phase.
Traditional, prior art embodiments of N step phase rotators employ control signals including N bits. As N (or the number of required phase interpolators) increases, the necessary control signal routing and congestion also increases. As this number increases, the digital to analog (I/F) interfacing becomes a challenging design issue.
In addition, the bandwidth limitation of typical transmission media creates Inter-Symbol Interference (ISI) which limits the receiver capability to correctly detect the transmitted data. To address this problem, some prior art approaches have employed equalizers that are often integrated into such communication receivers.
A digital signal processor (DSP)-based equalizer is usually the preferred choice in the prior art because of its increased flexibility and better performance compared to an analog implementation. To enable such equalizers, a high speed analog-to-digital converter (ADC) is required. Time-interleaved ADCs have become the architecture of choice in the prior art for achieving such high conversion.
In time-interleaved ADCs, several sub-converter channels are operated in parallel such that each channel is running at a lower sampling rate than the rate of the incoming signal. One of the critical issues for such an implementation is to deal properly with the errors due to timing mismatch between the multiple channels performing digital sampling. A continuous scheme, based on multiple phase interpolators (PI) to adjust the sampling time of each ADC independently can correct for this timing mismatch. An approach employing a prior art phase interpolator is described below.
FIG. 2 illustrates an embodiment of a prior art phase interpolator 200. This diagram shows the block diagram of a traditional/prior art 4 stage time-interleaved ADC with four phase interpolators (PIs). The PIs receive clocks with different phases (an in-phase clock, clkI, and a quadrature clock, clkQ) and generate the main clock (e.g., of the output signal) which is the weighted sum of the input clocks determined by the value of pictrl. The number of bits needed is determined by the resolution (e.g., step size) necessary to minimize the dithering jitter in this example is 256 bits.
In this diagram, a 256 bit control signal is generated by each corresponding PI controller (e.g., depicted by digital control blocks) and fed directly to the corresponding PI. For a 4 stage time interleaved ADC, 1024 (=256×4) pictrl control lines are required. Such large number of lines increases the silicon area/real estate of a communication device and creates a significant number of problematic issues at the digital/analog interface. Also, any unwanted glitches may undesirably, and unpredictably, change the output phase.
This prior art approach to perform phase interpolation inherently includes a very large control word (e.g., 256 bits in this embodiment). This can consequently lead to significant congestion and consumptive of real estate within this prior art approach.
FIG. 3 illustrates an embodiment of a prior art phase interpolator 300. To reduce the number of control lines at the digital-analog interface (I/F), a corresponding decoder can be implemented in the analog domain as shown in the diagram for each corresponding phase interpolator (PI). In this approach, there are two signals (e.g., up/down signals) employed per PI at the digital interface. It is noted, however, that the up/down signals need to be sampled before each corresponding decoder. Since the frequency of the sampling clock (ctrlclk) is much less than high-speed clock input, the latency of the clock recovery (CR) loop increases, thereby increasing jitter peaking.
As can be seen when considering the prior art scheme, there is a great deal of control signaling and routing therein. There exists a need in the art a better means by which phase interpolators may be implemented.